debug

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debug

to identify and remove errors from a COMPUTER program.

References in periodicals archive ?

In contrast to it, this paper presents one method which only some SFR (special function register) needed to realize the main debugging functions such as single step operation, breakpoint, etc.

Architecture and design methodology of on-chip debug module for multi-cores system

We're pleased to announce the availability of ThreadX kernel-aware debugging integrated into our Eclipse-based Navigator IDE," said Rick Leatherman, vice president and general manager of FS2.

Express Logic's ThreadX(R) RTOS Gains MIPS(R) SDE Kernel-Aware Debug Support

By marketing TotalView, as well as making it available at our Deep Computing Capacity on Demand centers, we have another capability that can help empower our customers to meet the rigorous debugging demands of these powerful systems.

Etnus to Offer TotalView(R) Debugger on IBM Deep Computing Solutions

NASDAQ:WIND), the global leader in Device Software Optimization (DSO), today announced the immediate availability of a new multicore on-chip debugging solution for the Intel IOP342 processor.

Wind River Debuts Multicore On-Chip Debugging Support for Intel IOP342 Processors

1) technology, Optima(TM) provides advanced system level browsing, debugging, profiling and analysis tools that greatly simplify the debugging and optimization of large-scale distributed systems spanning multiple processors and operating systems.

Enea Announces Eclipse-Based Integrated Development Environment for OSE RTOS

The Nexus 5001 standard is the only open debugging standard in the world and addresses the emerging multi-processor debugging problems of embedded systems with a common interface.

Analog Devices, NEC Electronics, Tensilica, and Texas Instruments Join Nexus 5001(TM) Forum; Consortium Driving Real-Time Development Tool Interface That is Engineered for Multi-Core Debug for Reduced Development Cycle Time

This new debugging capability on the PICkit 2 greatly enhances the ability of our customers to get to market faster with an extremely small investment of money and time.

Microchip Technology Announces Debugging Capability for Low-Cost Development Programmer; PICkit(TM) 2 Debug Express Enables Quick Learning of PIC(R) Microcontrollers

This option provides a great degree of flexibility -- since tokens can be aggregated to debug an application with many processes, or distributed for routine debugging of many smaller jobs.

Etnus Announces Flexible Licensing, Exchange Credit for TotalView(R) Debugger; Also Releases New Product for Debugging on Laptops and Workstations

This gives developers designing with ColdFire an advanced, embedded tool suite for developing, compiling, debugging, and deploying embedded applications, quickly and cost-efficiently.

Mentor Graphics EDGE Tool Suite Supports Freescale ColdFire Microprocessors and Microcontrollers

FREIBURG, Germany -- Concept Engineering today announced the release of SGvision(TM) PRO, a mixed-mode debugging tool that allows system-on-chip (SoC) designers and verification engineers to more quickly analyze and debug circuits that contain both digital and transistor-level components.

Concept Engineering Introduces SGvision(TM) PRO to Help System-on-Chip Designers Analyze and Debug Mixed-mode Circuits; Tool Provides Detailed Information for Both Digital and Analog or Library Components

1V1, our customers can count on Vista's debugging capabilities regardless of the version of the SystemC being used.

Summit Design's Award Winning Vista IDE Enhances Its SystemC Debugging Capabilities With IEEE 1666 and Windows Platform Support; Vista 2006.1 Provides Easier Integration With Third-Party Tools and SystemC Design Environments

the leader in debug systems for complex chip designs, today introduced a new set of capabilities that streamline the process of analyzing and debugging assertion failures for users of SystemVerilog Assertions (SVA).

Novas Enhances Assertion Debug Capability for SystemVerilog Users; Debug Leader Introduces Automation Features to Streamline Process for Understanding Assertion Failures in Complex Designs