Using an external data acquisition device to off load interrupt requests required of the microprocessor will reduce overall system power.
Using a CPLD to handle data acquisition interrupts will off-load interrupt requests to the microprocessor and save power.
Peripheral devices or incoming data demanding a response to incoming data can be classified as data acquisition interrupt requests. Data acquisition interrupts include memory access interrupts, communication interfaces, general-purpose I/O interrupts and LCD interface interrupts.
The low power CPLD design consists of an interrupt interface and controller to handle interrupt requests, the functionality to process the interrupt and a processor interface.
The interrupt interface of the CPLD receives all external device interrupt requests previously recognized by the microprocessor.
The CPLD provides the interface to system devices that are needed in processing interrupt requests. Device interfaces that are needed are dependent on the end application.