# Y

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## Y

Fifth letter of a Nasdaq stock symbol specifying that it is an ADR

## Y

A symbol appearing next to a security listed on NASDAQ indicating that the security is an American Depository Receipt. All NASDAQ listings use a four-letter abbreviation; if a "Y" follows the abbreviation, this indicates that the security being traded is an ADR.
References in periodicals archive ?
As previously explained, the individual results of the modules are put together using a combinational logic to obtain a final result of diagnosis.
The multiplexer is a combinational logic device, which receives several input variables and selects one of them to be its output (Mano & Dime, 1997).
Where [T.sub.CLK] = clock period, [T.sub.SETUP] = setup time [T.sub.HOLD] =hold time, [D.sub.MAX] = longest path delay between combinational logic, [T.sub.SKEW] = clock skew Even conventional pipelined technique improve the throughput of the digital systems it has some drawbacks such as increase in latency and area due to placing of latch/register between every logic[1], clock distribution ,clock skew [2].
For a combinational logic circuit, we first duplicate the whole circuit.
Aguirre, ""Automated Design of Combinational Logic Circuits Using Genetic Algorithms", in Proc.
Blaauw, "Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors," IEEE Trans.
As expected, the combinational logic area and the power consumption of the [mu]-CORDIC PE are much smaller than the Full CORDIC.
Cavanagh (computer engineering, Santa Clara U.) makes good use of his decades of experience as he focuses on the practical aspects of creating state machines while giving readers sufficient theory to understand what they are doing, starting by reviewing combinational logic, including number systems, number representations, Boolean algebra, minimization, logic symbols, analysis and synthesis of combinational logic, multiplexers, decoders, encoders, comparators, storage elements, and programmable logic devices.
This paper has proposed a power gating technique that reduces leakage power during the active mode for low performance energy-constrained applications by power gating combinational logic within the clock period.
Sequential circuits are more likely to be affected by HT effect propagation, as latches and flip-flops have a higher probability to remain high with short-circuit power than combinational logic gates.
Specific topics include reliability issues for embedded SRAM at 90nm and below, test challenges for 3D circuits, combinational logic soft-error analysis, and online error detection in wireless RF transmitters using real-time streaming data.
However, in this work the main target is using the MUX based AOI in conjunction with combinational logic that result in less area, memory, Power and delay.
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