Wafer Seal

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Wafer Seal

A small adhesive, shaped like a wafer, that holds the pages of a magazine or other periodical together when it is sent in the mail. A wafer seal may also be placed on an envelope. Its purpose is to ensure that one does not read the enclosed material without leaving evidence of doing so. It is also called a mailing tab.
References in periodicals archive ?
If you continue beyond that point, you reach the supercritical phase, where you have something with the density of a liquid but many of the properties of a gas--no surface tension, low viscosity, the ability to diffuse into anything, including the bond that the photoresist forms with the semiconductor wafer surface.
Scorr one for the environment. (Innovations)
The system's UV wavelength confines the laser beam to the wafer surface, minimizing false counts from buried defects.
KLA-Tencor's New Surfscan SP2XP Wafer Inspection System Combines Highest Sensitivity and Throughput to Enable 45nm Generation Defect-Free Wafers
Etsuro Morita, General Manager of SUMCO Production and Technology Division, said, "Our partnership with KLA-Tencor will help us to move to the next-generation of wafer manufacturing and beyond, where our customers are building nanometer-scale devices on substrates of a higher quality than ever before.
KLA-Tencor's Latest Inspection Technology Helps Top Wafer Manufacturers Improve Defect-Free 45-nm Generation Wafer Production
Available in both 200mm and 300mm wafer sizes, Integral Wafer utilizes SensArray's existing Thermal Map software application for data display and analysis and the BaseStation and CarrierStation for production deployment and storage.
SensArray Introduces Integral Wafer for Plasma, Wet and Planarization Processes; Breakthrough ''Zero Profile'' Architecture Produces Wireless Metrology Wafer Capable of Surveying Severe Process Environments
Up to 21 process modules (42 wafer process positions) can be configured in any combination, thus permitting virtually limitless process variations to meet changing demands.
The New Stratus 200 and Stratus 300 Provides Highest Throughput Electrodeposition System with Maximum Wafer Yield
ADE Corporation is a leading supplier of metrology and inspection systems for the semiconductor wafer, semiconductor device, magnetic data storage and optics manufacturing industries.
ADE Receives Large Multi-Million Dollar Order From Major Japanese Silicon Wafer Supplier; Inline Wafer Metrology Systems to Support 300mm Capacity Expansion
Silicon-on-Insulator (SOI) refers to a substrate technology where an insulating layer is formed within a silicon wafer, isolating the thin top layer of silicon where the active transistors will be manufactured from the rest of the silicon substrate.
Ibis Technology Announces Final Customer Acceptance of Oxygen Implanter; SUMCO grants final acceptance for their first Ibis i2000 implanter, while their second i2000 prepares for factory acceptance testing at Ibis
Wafer suppliers and device manufacturers worldwide rely on ADE inspection and measurement systems to certify and ensure the highest quality bare silicon substrates.
ADE Receives Multi-Tool Order From Major Asian Silicon Wafer Supplier; Inline Wafer Metrology Systems to Support Ongoing 300mm Capacity Expansions
Elpida's state-of-the-art semiconductor wafer manufacturing facilities are located in Hiroshima, Japan.
Hiroshima Elpida Commences Mass Production of 90 nm DRAM Chips on New 300 mm Wafer Production Line; Newly Expanded E300 Fab Targets 54,000 Wafers per Month, the Largest Semiconductor Capacity in Japan
Separation-by-IMplantation-of-OXygen (SIMOX) refers to a technique used by Ibis for manufacturing SOI wafers where an oxygen implanter creates a very thin insulating layer within the wafer, just below a thin layer of silicon on the top of the wafer.
Ibis Technology Receives Implanter Order; SUMCO Orders Second Ibis i2000 Oxygen Implanter
A truly unique dimension Cubic Wafer offers is our ability to bring relevance to Moore's Law using today's technology," said Ed Healy, chief executive officer of Cubic Wafer.
Ed Healy and Abhay Misra Join Cubic Wafer Management Team; Austin Company Enables Dense Vertical Integration (3D Chips) and Restores Moore's Law for the Integration Possibilities of the Semiconductor Industry
These options include special end effectors to address thin, double sided, and glass wafer handling as well as OCR and barcode readers for wafer identification and traceability.
Chad Industries Showcases New WaferMate(TM) Wafer Handling Workcell at Semicon West 2005; WaferMate(TM) Workcells Designed to Seamlessly Integrate with Fab and Assembly Equipment
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