The Cortex-A9 power-optimized hard macro
implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
QuickLogic's Hard Macro
tool, coupled with their uWatt FPGAs and Programmable Bridges, enables Quest Innovations to ensure our customers meet these market demands.
Socle and ICC combine the ZSP400 hard macro
with their own IP to complete a SoC platform.
By offering the 440T90 hard macro
, GDA provides a flexible platform and offers exceptional value to customers wanting to develop SOC designs for a variety of markets," said Tom Quan, Deputy Director, Design Services Marketing at TSMC.
The new patented placement algorithm in the JupiterXT solution automatically places both hard macros
and standard cells, which also eliminates manual iterations.
It can automatically perform mixed- size placement of multimillion-instance designs with hundreds of hard macros
Chip data setup is similar to other chip design software -- DEF for chip netlist, intellectual property (IP) libraries for I/O, standard cell and hard macros
in LEF and I/O driver models in IBIS.
The ZSP Processing Solutions are available as licensable, synthesizable cores and hard macros
, as well as off-the-shelf general purpose DSP, multi-channel voice processors and application specific standard products from LSI Logic and ZSP licensees.
It allows us to create an automatic floorplan for multi-million gate designs with hundreds or even thousands of hard macros
in minutes or hours, as opposed to the days or weeks it formerly took.
All True Circuits high-quality, low-jitter, silicon-proven hard macros
are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in 0.
These high quality low-jitter, silicon-proven hard macros
benefit from Virtual Silicon's experience in delivering reliable frequency synthesizers for complex SoCs.
Delivered as two hard macros
, it is used for flat panel displays in laptop computers.