The Cortex-A9 speed-optimized hard macro
implementation will provide system designers with an industry standard ARM[R] processor incorporating aggressive low-power techniques to further extend ARM's performance leadership into high-margin consumer and enterprise devices within the power envelope necessary for compact, high-density and thermally constrained environments.
The hard macro
solutions resulting from the collaboration are expected to enable systems and semiconductor companies to use SMIC's foundry process with minimum integration cost, accelerated integration time and reduced risk.
QuickLogic designers can now use the Hard Macro
tool to "harden" the Verilog or VHDL intellectual property content with embedded placement information.
These high quality, low-jitter PLL and DLL hard macros
are suited to a wide variety of interface standards and chip applications.
Chip data setup is similar to other chip design software -- DEF for chip netlist, intellectual property (IP) libraries for I/O, standard cell and hard macros
in LEF and I/O driver models in IBIS.
It allows us to create an automatic floorplan for multi-million gate designs with hundreds or even thousands of hard macros
in minutes or hours, as opposed to the days or weeks it formerly took.
All True Circuits high-quality, low-jitter, silicon-proven hard macros
are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in 0.
These high quality low-jitter, silicon-proven hard macros
benefit from Virtual Silicon's experience in delivering reliable frequency synthesizers for complex SoCs.
Delivered as two hard macros
, it is used for flat panel displays in laptop computers.