The size of the buffer is driven by the difference between the input and output clocking speeds, the buffering
time required by the system, and the bus width.
The CY7C08D53 provides 9 Mbits of synchronous, pipelined dual-ported memory capable of buffering
large packets of data in two independent clock domains.
This ultra-low-power design, available in the tiny SOT23-6 package, is ideal for buffering
reference voltage in TFT-LCD applications.
Secondly, is the issue of SAN switch designs which did not provide enough buffering
to mask the amount of time, or latency, it takes to "fill" a long distance link with data and allow it to be continuously fed with data.
enables non-blocked switching of 24 million Ethernet packets per second without expanding to off-chip overflow buffering
18-micron process technology, these new processors feature Advanced Transfer Cache and Advanced System Buffering