The typical large die flip
chip package assembly process consists of several steps: 1) flip chip die flux and place, 2) solder bump reflow, 3) underfill and cure, 4) heat spreader/lid attach and cure, 5) BGA ball attach and reflow.
The
chip packages feature ACA's logo and a statement about the camp experience.
Intel officials have said they wanted to make smaller
chip packages so PC makers can design thinner netbooks.
Not expected to be discussed is an exemption for lead in solders consisting of more than two elements for the connection between the pins and the package of microprocessors with a lead content of more than 80% and less than 85% by weight; lead in solders for electrically connecting semiconductor die and carriers within flip
chip packages; or lead in finishes of fine-pitch components other than connectors with a pitch of 0.65 mm or less with NiFe lead frames, and lead in finishes of fine pitch components other than connectors with a pitch of 0.65 mm or less with copper lead frames.
Most
chip packages being shipped today use a layer of tin and lead over copper.
The Paper Thin Package (PTP) technology reduces the size of stacked
chip packages by shrinking the width of the individual stacked ICs.
The high power LED market for flip
chip packages will grow at the highest CAGR during the forecast period owing to its advantages over the traditional horizontal mesa packaging and vertical packaging.