Timing option

Timing option

The seller's choice of when in the delivery month to deliver. A Treasury Bond or note futures contract.

Timing Option

The ability of the seller of a Treasury security or futures contract to decide at what point in the delivery month actual delivery shall be made.
References in periodicals archive ?
The company noted that the motor also includes a field adjustable timing option as a standard feature.
The Time Interval/Event Timing option enables the XLi to precisely measure the interval between the XLi's 1 PPS pulse and the rising edge of the user-supplied 1 PPS pulse.
The Frequency Measurement Option is $660, the Time Internal/Event Timing Option is $660 and the Programmable Pulse Option is $360.
The critical timing option supports the characterization and production test of timing-critical PLL and advanced bus technologies found in today's generation of microprocessors and graphics chipsets.
In other clinical trials, Bull anal her team are investigating timing options for hyperthermia treatments and combining it with drugs.
Synthesizers Ideal Clock Source for Interface Cards Requiring Legacy Compatibility or Interface Card Timing Options
The Master Remote Control also features a variety of timing options, 12 "scenes," battery backup, 6 on/off features, visual feedback and an "Astro" feature that allows you to turn your lights on at sunset and off at sunrise without ever having to reset the timer.
The compiler allows the user to select specifications for the design, which include: memory size and configuration (number of words and word size operating parameters, speed and temperature range), interface timing options (pipelined or flow-through read access, as well as options on write timing) and choosing deliverable options.
This facility allows the avoidance of bad debt risk for sellers, options to accelerate cash flow for selling members and a range of payment timing options for buyers.
It provides user-selectable internal, external and slave/receive timing options.
35 micron level require exceedingly higher gate counts, larger pin counts, more complexity and increased chip level timing options.