This enables more efficient capture of design RTL with constructs such as multi-dimensional arrays, signed arithmetic extensions, 'generate' statement, combinational logic
sensitivity, and re-entrant tasks and functions.
Generate statement -- File I/O enhancements -- Inclusion of attribute properties -- Constraints for negative timing check -- Definitions for ANSI C style ports, task and function I/O -- Explicit in-line parameter passing -- Comma separated sensitivity lists -- Wild card for combinational logic
optimization that automatically focuses specific optimizations on areas of the design that likely hinder overall performance, such as finite state machines (FSM), cross-hierarchical paths, or paths with excessive combinational logic
For small design changes, such as adding or modifying combinational logic
, this is usually one PLD, which makes the compilation turnaround time less than 30 minutes running on a single workstation.